Low-power integrated-circuit signal processor with wide dynamic range

ABSTRACT

An integrated circuit includes at least three separate power supply terminals, at least one for those portions of the circuit that must accommodate the widest signal-related voltage excursion, at least one for those that experience substantially smaller signal-related voltage excursions, and a common terminal.

RELATED APPLICATION

This application is related to provisional application Ser. No.60/510,491 filed Oct. 10, 2003.

FIELD OF THE DISCLOSURE

This disclosure relates to analog and mixed-signal integrated circuits(ICs) that require wide dynamic range while minimizing power consumptionand power-supply complexity. More specifically, it relates to analog andmixed-signal ICs that require wide dynamic range while operating fromlow power-supply voltages, such as those typically encountered inbattery-powered devices.

BACKGROUND OF THE DISCLOSURE

The dynamic range of analog information signal-processing circuits isinherently constrained by circuit noise, which obscures the smallestinformation signals, and power supply limitations, which limit thelargest information signals that can be processed accurately. Manyapplications, especially portable, battery-powered audio products,require wide dynamic range and simultaneously low-power operation fromlow-voltage power supplies.

A particular class of applications involves conditioning the outputvoltage from a transducer or sensor. It is often advantageous to amplifythe output voltage from such a source prior to further signalprocessing. It is also often advantageous to terminate such a sourcewith a specific load impedance to maximize its signal-to-noise ratioand/or tailor its frequency response. These functions are typicallyaccomplished by a preamplifier. In systems operating from lowpower-supply voltages, it is often desirable for the circuit to performfurther signal processing on currents representative of the preamplifieroutput, rather than voltages. As is well known in the art, manycurrent-mode, signal-processing circuits have been developed thatminimize signal-related voltage excursions in the circuit. Suchcircuits, if designed to operate in class AB, also consume little powersupply current under quiescent conditions. This makes them particularlydesirable for battery-powered applications.

When such a signal-processing system is implemented in integratedcircuit form, all sections of the circuitry typically operate from asingle pair of power supply terminals. In this case, the power supplyvoltage of the entire IC must be set to accommodate the maximumpreamplifier output voltage necessary to achieve the desired dynamicrange. In systems with wide dynamic range requirements, this results inother parts of the circuitry, such as current-mode signal processingcircuits, operating at a higher-than-necessary power-supply voltage.

SUMMARY OF THE DISCLOSURE

In accordance with the present approach, at least three separate powersupply terminals are provided on an integrated circuit, at least onecoupled solely to those portions of the circuit that must accommodatethe widest signal-related voltage excursion and at least one coupledsolely to those that experience substantially smaller signal-relatedvoltage excursions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a preferred embodiment of an analogintegrated circuit with a common positive power supply terminal, aground terminal, which serves as the negative power supply terminal fora current-mode signal-processing section, and a separate negative powersupply terminal for an input-voltage preamplifier.

FIG. 2 is a block diagram of a preferred embodiment of an analogintegrated circuit with a one positive power supply terminal for acurrent-mode signal-processing section, a separate second positive powersupply terminal for an input-voltage preamplifier, and a common groundterminal, which serves as the negative power-supply terminal for bothsections.

FIG. 3 is a block diagram of a preferred embodiment of an analogintegrated circuit with three power supply terminals similar to thatshown in FIG. 1, and further including a syllabic compressor.

FIG. 4 is a block diagram of another embodiment of an analog integratedcircuit.

FIG. 5 is a block diagram of a preferred embodiment of an analogintegrated circuit, and further including a syllabic expander.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram an integrated circuit, 11, with a commonpositive power-supply terminal for an input voltage preamplifier and acurrent-mode signal-processing section and separate negativepower-supply terminals for the input-voltage preamplifier circuitry andcurrent-mode signal-processing section. In this embodiment, preamplifier2 receives a positive power-supply voltage Vcc via terminal 5 and anegative power supply voltage Vee via terminal 6. Preamplifier 2 acceptsan input voltage from terminal 1. Its output voltage, at terminal 4,will be capable of positive excursions up to close to the positivesupply voltage Vcc and negative excursions up to close to the negativesupply voltage Vee. If Vcc and Vee are equal in magnitude, the availabledynamic range at preamplifier 2's output is increased by about 6 dB overthe dynamic range available when the preamplifier 2 is operated usingonly the power supply voltage Vcc. The output voltage from preamplifier2 is coupled to the input of current-mode signal processing block 3 viacurrent-to-voltage conversion resistor R1 and ac-coupling capacitor C1.Signal-processing block 3 also receives the positive power-supplyvoltage Vcc via terminal 5. Its negative power supply terminal isconnected to the reference potential, or ground, via terminal 9. As istypical of such current-mode circuits, signal-processing block 3 isdesigned to have a low-impedance input (virtual ground) accepting inputcurrents. In this embodiment, input terminal 7 of the current-modesignal processing block 3 preferably has a dc bias potential between Vccand Ground. Preamplifier 2 preferably is designed to have a dc biaspotential half way between Vcc and Vee in order to maximize the possiblevoltage swing at its output. Ac coupling capacitor C1 blocks dc currentsthat would result from the differing dc bias potentials at terminals 4and 7. Such currents would increase the supply current of the IC andpotentially reduce the dynamic range of current-mode signal-processingblock 3, particularly if signal-processing block 3 is a class ABcircuit. Note that it is assumed that output 10 is a current orotherwise does not require large voltage excursions. If a large voltageswing were required at this output, a current-to-voltage converter thatoperated from Vcc and Vee could be added to produce an output voltagefrom the current-mode signal-processing block's output.

The embodiment in FIG. 1 is well suited to applications that utilizeother integrated circuits that operate from a single positive powersupply, such as most digital logic circuits. In this case, the positivepower supply voltage, Vcc, would be shared by all of the ICs. Thenegative power-supply voltage for the preamplifier, Vee, can begenerated from the positive power supply Vcc, for example, by aswitched-capacitor voltage inverter. Since such an inverter must supplyonly the supply current for preamplifier 2, the required capacitors forthe inverter can be relatively small. With an appropriate semiconductorprocess, such an inverter may be integrated into the integrated circuit11, resulting in very low power-supply complexity for the application.

FIG. 2 shows a block diagram of an integrated circuit, 11, with twoseparate positive power supply terminals for providing different powersupply voltages to the input-voltage preamplifier circuitry and thecurrent-mode signal-processing circuitry. In this embodiment,preamplifier 2 receives positive power-supply voltage Vcc1 via terminal5. Its negative power supply terminal, along with that of current-modesignal-processing block 3, is connected to a reference potential, orground (as shown in the Figure), via terminal 9. Preamplifier 2 acceptsand input voltage from terminal 1. Its output voltage, at terminal 4,will be capable of positive excursions between a value close to thepositive supply voltage Vcc1, and a value close to ground. A secondsupply voltage Vcc2 is applied through the terminal 6 to thecurrent-mode signal processing block 3. Power supply voltage Vcc1 ischosen to be greater than power supply voltage Vcc2 in order to allow alarge voltage excursion at the output of preamplifier 2. The outputvoltage from preamplifier 2 is coupled to the input of current-modesignal processing block 3 via current-to-voltage conversion resistanceR1 and ac coupling capacitor C1. The negative power supply terminal ofsignal processing block 3 is connected to the reference potential, orground, via terminal 9. Current-to-voltage conversion resistor R1 andac-coupling capacitor C1 function as described above for FIG. 1. Again,the output from current-mode signal processing block 3 is assumed torequire small voltage excursions. A current-to-voltage converteroperating from Vcc1 and ground could be added to produce an outputvoltage from the current-mode signal-processing block's output.

The embodiment in FIG. 2 is also well suited to applications thatutilize other integrated circuits that operate from a single positivepower supply, such as most digital logic circuits. In this case, thepositive power supply voltage, Vcc2, would be shared by all of the ICs.The positive power-supply voltage for the preamplifier, Vcc1, can begenerated from the positive power supply voltage Vcc1 via a charge pump.Since this charge pump must supply only the supply current forpreamplifier 2, the required capacitors can be relatively small. With anappropriate semiconductor process, such a charge pump may be integratedinto the integrated circuit 11, resulting in very low power-supplycomplexity for the application:

The choice between an embodiment similar to FIG. 1 and one similar toFIG. 2 would be made based, in part, on the design of thewide-voltage-swing circuitry that operates from the additional supplyvoltage. If the second supply voltage is generated by a charge pump or acapacitive voltage inverter, it is likely to be noisier than the primarypower supply Vcc or Vcc1. As is well known in the art, many amplifiercircuits exhibit better power-supply rejection from one power supplyterminal than the other. Thus, it is advisable to design the integratedcircuit such that the additional power supply voltage is connected tothe terminal of the wide-voltage-swing circuitry that exhibits the bestpower supply rejection ratio.

It should be understood that an embodiment which incorporates powersupply terminals for both the positive and negative power supplyconnections of the circuitry requiring large signal voltage swingsseparate from the power supply connections to the rest of the integratedcircuit may be implemented in accordance with teachings of thisdisclosure. Such an implementation would increase the maximum dynamicrange available for voltage signals, at the expense of addedpower-supply complexity and an additional terminal on the integratedcircuit 11.

Wireless microphone systems are one such application where such anintegrated circuit, such as described in connection with FIG. 1 or FIG.2 may used to an advantage. In the majority of such systems, an analogvoltage, representative of the sound (acoustic signal) picked up by amicrophone capsule, is amplified, subjected to various types of signalconditioning, and then transmitted via a radio-frequency (RF) carrier toa remotely located receiver. It is important that the circuitry in thetransmitter be compact and lightweight, as it is typically located inthe case containing the microphone capsule, which is often handheld orworn by a performer. As batteries are a major component of the size andweight of this package, low-power, and, preferably, low-voltagecircuitry is a requirement. Wide dynamic range is also a requirement,since the dynamic range of human hearing is on the order of 120 dB.

The signal-conditioning circuitry between the microphone capsule and anRF modulator in high-quality wireless microphone systems typicallycomprises a preamplifier, pre-emphasis and band-limiting filters, and acompressor circuit that functions as part of a syllabic compandingsystem. The preamplifier serves to amplify the output voltage from thecapsule (the audio signal), and to terminate it with an appropriate loadimpedance. This preamplifier should preferably have low input-referrednoise so as to degrade the signal-to-noise ratio of the capsule outputas little as possible. The preamplifier should also provide enough gainso that the noise contributions of subsequent circuitry in the signalpath will be negligible. As is well known in the art, the pre-emphasisfilters serve to further amplify high-frequency components of the audiosignal so that they will be substantially higher in level than the noiseadded by the RF channel. A complementary de-emphasis filter in thereceiver serves to restore flat overall frequency response in the audiobandwidth, and simultaneously attenuate the noise. The syllabiccompander is another well-known approach to preserve dynamic range whennoise is added to the signal of interest, in this case by the RFchannel. Typically, such systems include a compressor circuit ahead ofthe noisy channel, and a complementary expander at the output of thenoisy channel. A typical compressor circuit includes, at a minimum, avariable-gain element and a level detector. The gain of thevariable-gain element in the compressor circuit is varied in response tothe output of the level detector such that gain is decreased as thelevel of the signal of interest increases, and the gain is increased asthe level of the signal of interest decreases. This serves to keep thesignal of interest substantially higher in amplitude than the additivenoise of the channel, and to minimize any occasions when the signal ofinterest may exceed the maximum possible amplitude that the channel canaccommodate without excessive distortion. The expander circuit functionsin a complementary fashion to restore the original dynamics to thesignal of interest.

FIG. 3 shows a block diagram of an embodiment of an integrated circuitintended for use as a signal processor for wireless microphones andincluding the architecture of the type previously described. In thisembodiment, preamplifier 2 receives a positive power-supply voltage Vccvia terminal 5 and a negative power supply voltage Vee via terminal 6.Preamplifier 2 accepts an input voltage from terminal 1. Its outputvoltage, at terminal 4, will be capable of positive excursions up to avalue close to the positive supply voltage Vcc and down to a value closeto the negative supply voltage Vee. If Vcc and Vee are equal inmagnitude, the available dynamic range of the output of preamplifier isincreased by about 6 dB over the dynamic range available when it isoperated from Vcc alone.

Current-mode compressor block 3 receives a positive power-supply voltageVcc via terminal 5. Compressor block 3 has a negative power supplyterminal connected to a reference potential, or ground, via terminal 9.Current-mode compressor block 3 comprises at a minimum a variable-gainelement and a level detector. The gain of the variable-gain element inthe compressor circuit is varied in response to the output of the leveldetector such that gain is decreased as the level of the signal ofinterest increases, and the gain is increased as the level of the signalof interest decreases. The output voltage from preamplifier 2 is coupledto the input of current-mode compressor block 3 via current-to-voltageconversion resistor R1 and ac coupling capacitor C1. AC couplingcapacitor C1 blocks dc currents that would result from the differing dcbias potentials at terminals 4 and 7. The variable-gain element incompressor 3 receives an input current via terminal 7. Input terminal 7is preferably a low-impedance virtual ground with a dc bias voltagebetween Vcc and ground. The output voltage from preamplifier 2 iscoupled to the input of current-mode compressor block 3 viacurrent-to-voltage conversion resistor R1 and ac coupling capacitor C1.Ac coupling capacitor C1 blocks dc currents that would result from thediffering dc bias potentials at terminals 4 and 7. Resistor R2 andcapacitor C2 forms a type of preemphasis network that increases thelevel of input currents in the variable gain block of compressor 3 athigh frequencies.

The output current of the variable gain element in current-modecompressor block 3 is coupled to the inverting input ofcurrent-to-voltage conversion opamp 11, which is externally accessiblethrough terminal 10. The output of the opamp 11 is externally accessiblethrough the terminal 12. The non-inverting input of opamp 11 isinternally connected to a reference voltage, Vref. The latter ispreferably between positive supply voltage Vcc and ground. The externalcurrent-to-voltage conversion resistor R3 is connected between theterminal 10 and the terminal 12, thus forming a feedback resistor forthe opamp 11, and determines the scaling of the output voltage producedin response to and as a function of the output current from compressorblock 3. As is well known in the art, this configuration of feedbackthrough the resistor R3 around opamp 11 creates a low-impedance virtualground at the inverting input of opamp 11. Note that since the outputvoltage produced by opamp 11 is compressed due to the action ofcompressor block 3, the output voltage swing may be substantially lessthan that at the output of preamplifier 2 without loss of dynamic range.Thus, in this embodiment, opamp 11 can operate between supply voltageVcc and ground.

The output of opamp 11 is coupled to the detector input of current-modecompressor block 3 at the terminal 16 via voltage-to-current conversionresistor R4 and ac coupling capacitor C4. Detector input terminal 16 ispreferably a low-impedance virtual ground with a dc bias potentialbetween Vcc and ground. Resistor R4 and capacitor C4 function similarlyto resistor R1 and capacitor C1. As is well known in the art, the leveldetectors utilized in syllabic companders respond to a time-weightedaverage of some measure of the magnitude of the signal of interest.Capacitor C3, connected between compressor block 3 and ground viaterminal 15, along with internal circuitry, implements the largeaveraging time constant for the detector as is well known. For syllabiccompanding of audio-band signals, the time constant is preferably on theorder of several 10's of milliseconds, which can require capacitancesthat are impracticably large for integration. Alternatively, for otherapplications it may be possible to include these capacitances andresistances as a part of the integration.

In the embodiment of FIG. 3, the output of opamp 11 is also preferablycoupled to filter block 13. Filter block 13 serves to bandlimit theoutput signal as necessary prior to RF modulation. As mentioned above,since the output signal from opamp 11 is compressed, the filtercircuitry in block 13 may function on signal voltages, as opposed tocurrents, while still operating from positive supply voltage Vcc andground without compromising dynamic range. Filter block 13 could also beimplemented as a current-mode circuit. In this case, it would preferablybe placed between compressor block 3 and opamp 11.

FIG. 4 shows a block diagram an integrated circuit, 11, with a commonpositive power-supply terminal for a current-mode signal-processingsection and an output current-to-voltage converter, and separatenegative power-supply terminals for the current-mode signal-processingsection and the output current-to-voltage converter. In this embodiment,current-mode signal-processing block 3 receives a positive power-supplyvoltage Vcc via terminal 5. Its negative power supply terminal isconnected to the reference potential, or Ground, via terminal 9.Current-mode signal-processing block 3 accepts an input current fromterminal 1. As is typical of such current-mode circuits,signal-processing block 3 is designed to have a low-impedance input(virtual ground) accepting input currents. In this embodiment, inputterminal 1 of the current-mode signal-processing block 3 preferably hasa dc bias potential between Vcc and Ground. 2 Current-to-voltageconverter 17 accepts output current from signal-processing block 3 andproduces an output voltage proportional to this current at terminal 10.As is typical of such circuits, current-to-voltage converter 17 isdesigned to have a low-impedance input (virtual ground) accepting inputcurrents. Current-to-voltage converter 17 also receives a positivepower-supply voltage Vcc via terminal 5 and a negative power supplyvoltage Vee via terminal 6. Its output voltage, at terminal 10, will becapable of positive excursions up to close to the positive supplyvoltage Vcc and negative excursions up to close to the negative supplyvoltage Vee. If Vcc and Vee are equal in magnitude, the availabledynamic range at preamplifier 2's output is increased by about 6 dB overthe dynamic range available when the current-to-voltage converter 17 isoperated using only the power supply voltage Vcc. Current-to-voltageconverter 17 preferably is designed to have a dc bias potential at itsoutput half way between Vcc and Vee in order to maximize the possiblevoltage swing at its output.

FIG. 5 shows a block diagram of an embodiment of an integrated circuitintended for use as a expander for such devices as wireless in-earmonitors. Such devices typically employ syllabic expanders around an RFchannel similar to that described above for wireless microphones. Inthis case, however, the receiver portion, including the syllabicexpander, may be a portable, battery-powered portion of the system wornby a performer. In this embodiment, current-to-voltage converter opamp11 receives a positive power-supply voltage Vcc via terminal 5 and anegative power supply voltage Vee via terminal 6. Current-to-voltageconverter opamp 11 accepts an input current from current-output expander18. Its output voltage, at terminal 14, will be capable of positiveexcursions up to a value close to the positive supply voltage Vcc anddown to a value close to the negative supply voltage Vee. If Vcc and Veeare equal in magnitude, the available dynamic range of the output ofpreamplifier is increased by about 6 dB over the dynamic range availablewhen it is operated from Vcc alone. Resistors R1 and R2, along withcapacitor C2 provide the current-to-voltage conversion impedance, withR2 and C2 implementing a high-frequency deemphasis that is preferablycomplementary to a preemphasis network employed in the transmitterportion in such a system.

Current-output expander 18 receives a positive power-supply voltage Vccvia terminal 5. Current-output expander 18 preferably has a negativepower supply terminal connected to a reference potential, or ground, viaterminal 9. Current-output expander 18 comprises at a minimum avariable-gain element and a level detector. The gain of thevariable-gain element in the expander circuit is varied in response tothe output of the level detector such that gain is increased as thelevel of the signal of interest increases, and the gain is decreased asthe level of the signal of interest decreases. Current-output expander18 receives an input signal at terminal 1. This input signal could be ineither current or voltage form, since the input signal will be expanded,and thus will require substantially less total excursion than theexpanded output voltage at terminal 14.

As is well known in the art, the level detectors utilized in syllabicexpanders respond to a time-weighted average of some measure of themagnitude of the signal of interest. Capacitor C3, connected betweencurrent-output expander 18 and ground via terminal 15, along withinternal circuitry, implements the large averaging time constant for thedetector as is well known. For syllabic expanding of audio-band signals,the time constant is preferably on the order of several 10's ofmilliseconds, which can require capacitances that are impracticablylarge for integration. Alternatively, for other applications it may bepossible to include these capacitances and resistances as a part of theintegration.

The embodiments and practices described in this specification have beenpresented by way of illustration rather than limitation, and variousmodifications, combinations and substitutions may be effected by thoseskilled in the are without departure either in spirit or scope from thisdisclosure in its broader aspects and as set forth in the appendedclaims.

1. An integrated circuit containing at least one analog circuitrysection for producing a final analog output information signal inresponse to a first analog input information signal, comprising: a firstanalog circuitry subsection that produces an intermediate analog outputvoltage in response to said first analog input information signal; asecond analog circuitry subsection that accepts an intermediate analoginput current proportional to said intermediate output voltage andproduces said final output information signal in response to saidintermediate analog input current; a first power-supply-voltage terminalcoupled to said first analog circuitry subsection; a secondpower-supply-voltage terminal coupled to said second analog circuitrysubsection; and a third power-supply-voltage terminal coupled to saidfirst analog circuitry subsection and said second analog circuitrysubsection; wherein the available dynamic range of said intermediateanalog output voltage is designed to exceed the difference in voltageapplied between said second and third power-supply terminals.
 2. Anintegrated circuit according to claim 1, wherein said first analogcircuitry subsection, first power-supply-voltage terminal and said thirdpower-supply-voltage terminal are configured so that in operation anegative voltage is applied to the first power-supply-voltage terminalwith respect to said third power-supply-voltage terminal, and saidsecond analog circuitry subsection, second power-supply-voltage terminaland third power-supply-voltage are configured so that in operation anegative voltage is applied to the second power-supply terminal withrespect to said third power-supply terminal.
 3. An integrated circuitaccording to claim 2, including a capacitive voltage inverter forproducing a negative power supply voltage in response to a positivepower supply voltage applied to said third power-supply-voltage terminalwherein said negative power supply voltage is connected to said firstpower-supply-voltage terminal.
 4. An integrated circuit according toclaim 1, wherein said first analog circuitry subsection, firstpower-supply-voltage terminal and said third power-supply-voltageterminal are configured so that in operation a positive voltage isapplied to the first power-supply-voltage terminal with respect to saidthird power-supply-voltage terminal, and said second analog circuitrysubsection, second power-supply-voltage terminal and thirdpower-supply-voltage are configured so that in operation a positivevoltage is applied to the second power-supply terminal with respect tosaid third power-supply terminal.
 5. An integrated circuit according toclaim 4, including a charge pump means producing a first positive powersupply voltage in response to a second positive power supply applied tosaid second power-supply-voltage terminal wherein said first powersupply voltage is connected to said first power-supply-voltage terminal,and where said first positive power supply voltage is greater than saidsecond power supply voltage.
 6. An integrated circuit according to claim1, wherein said second analog subsection is configured so as to producean analog output current in response to said intermediate analog inputcurrent.
 7. An integrated circuit according to claim 1, wherein saidsecond analog subsection is configured so as to produce a final analogoutput voltage in response to said intermediate analog input current,and said final analog output voltage is substantially less in totalexcursion than said intermediate output voltage.
 8. An integratedcircuit according to claim 1, wherein said second analog subsectionproduces a final analog voltage or current that is a syllabicallycompressed version of said intermediate output voltage.
 9. An integratedcircuit according to claim 8, wherein said second analog subsectionincludes: a variable gain means for producing said final analog outputvoltage in response to said intermediate input current; and a leveldetector means for producing a gain control signal in response to saidfinal analog output voltage; wherein the gain of said variable gainmeans responds to said gain control signal such that said gain isdecreased in response to an increase in said final analog output voltageor current and said gain is increased in response to a decrease in saidfinal analog output voltage or current.
 10. An integrated circuitaccording to claim 8, wherein said second analog subsection includes: avariable gain stage for producing said final analog output voltage inresponse to said intermediate input current; and a level detector forproducing a gain control signal in response to said final analog outputvoltage; wherein the gain of said variable gain stage responds to saidgain control signal such that said gain is decreased in response to anincrease in said intermediate input current and said gain is increasedin response to a decrease in said intermediate input current.
 11. Anintegrated circuit containing at least one analog circuitry section forproducing a final analog output information signal in response to afirst analog input information signal, comprising: a first analogcircuitry subsection that produces an intermediate analog output voltagein response to said first analog input information signal; a secondanalog circuitry subsection that accepts an intermediate analog inputcurrent proportional to said intermediate output voltage and producessaid final output information signal in response to said intermediateanalog input current; a first positive power-supply-voltage terminalcoupled to said first analog circuitry subsection; a second positivepower-supply-voltage terminal coupled to said second analog circuitrysubsection; a first negative power-supply-voltage terminal coupled tosaid first analog circuitry subsection; and a second negativepower-supply-voltage terminal coupled to said second analog circuitrysubsection; wherein the available dynamic range of said intermediateoutput voltage is designed to exceed the difference in voltage betweensaid second positive and second negative power-supply terminals.
 12. Anintegrated circuit according to claim 11, wherein said second analogsubsection is configured so as to produce an analog output current inresponse to said intermediate analog input current.
 13. An integratedcircuit according to claim 11, wherein said second analog subsection isconfigured so as to produce a final analog output voltage in response tosaid intermediate analog input current, and said final analog outputvoltage is substantially less in total excursion than said intermediateoutput voltage.
 14. An integrated circuit according to claim 13, whereinsaid second analog subsection is configured so as to produce an analogoutput current in response to said intermediate analog input current.15. An integrated circuit according to claim 13, wherein said secondanalog subsection is configured so as to produce a final analog outputvoltage in response to said intermediate analog input current, whereinsaid final analog output voltage is substantially less in totalexcursion than said intermediate output voltage.
 16. An integratedcircuit according to claim 11, wherein said second analog subsection isconfigured so as to produce a final analog voltage or current that is asyllabically compressed version of said intermediate output voltage. 17.An integrated circuit according to claim 16, wherein said second analogsubsection includes: a variable gain stage for producing said finalanalog output voltage in response to said intermediate input current;and a level detector for producing a gain control signal in response tosaid final analog output voltage; wherein the gain of said variable gainstage responds to said gain control signal such that said gain isdecreased in response to an increase in said final analog output voltageor current and said gain is increased in response to a decrease in saidfinal analog output voltage or current.
 18. An integrated circuitaccording to claim 16, wherein said second analog subsection includes: avariable gain stage for producing said final analog output voltage inresponse to said intermediate input current; and a level detector forproducing a gain control signal in response to said final analog outputvoltage; wherein the gain of said variable gain stage responds to saidgain control signal such that said gain is decreased in response to anincrease in said intermediate input current and said gain is increasedin response to a decrease in said intermediate input current.
 19. Anintegrated circuit includes at least three separate power supplyterminals, at least one for those portions of the circuit that mustaccommodate the widest signal-related voltage excursion, at least onefor those that experience substantially smaller signal-related voltageexcursions, and a common terminal.
 20. An integrated circuit containingat least one analog circuitry section for producing a final analogoutput voltage in response to a first analog input information signal,comprising: a first analog circuitry subsection that produces anintermediate analog output current in response to said first analoginput information signal; a second analog circuitry subsection thataccepts an intermediate analog input current proportional to saidintermediate output current and produces said final output voltage inresponse to said intermediate analog input current; a firstpower-supply-voltage terminal coupled to said first analog circuitrysubsection; a second power-supply-voltage terminal coupled to saidsecond analog circuitry subsection; and a third power-supply-voltageterminal coupled to said first analog circuitry subsection and saidsecond analog circuitry subsection; wherein the available dynamic rangeof said final analog output voltage is designed to exceed the differencein voltage applied between said first and third power-supply terminals.21. An integrated circuit according to claim 20, wherein said firstanalog circuitry subsection, first power-supply-voltage terminal andsaid third power-supply-voltage terminal are configured so that inoperation a negative voltage is applied to the firstpower-supply-voltage terminal with respect to said thirdpower-supply-voltage terminal, and said second analog circuitrysubsection, second power-supply-voltage terminal and thirdpower-supply-voltage are configured so that in operation a negativevoltage is applied to the second power-supply terminal with respect tosaid third power-supply terminal.
 22. An integrated circuit according toclaim 21, including a capacitive voltage inverter for producing anegative power supply voltage in response to a positive power supplyvoltage applied to said third power-supply-voltage terminal wherein saidnegative power supply voltage is connected to said secondpower-supply-voltage terminal.
 23. An integrated circuit according toclaim 20, wherein said first analog circuitry subsection, firstpower-supply-voltage terminal and said third power-supply-voltageterminal are configured so that in operation a positive voltage isapplied to the first power-supply-voltage terminal with respect to saidthird power-supply-voltage terminal, and said second analog circuitrysubsection, second power-supply-voltage terminal and thirdpower-supply-voltage are configured so that in operation a positivevoltage is applied to the second power-supply terminal with respect tosaid third power-supply terminal.
 24. An integrated circuit according toclaim 23, including a charge pump means producing a second positivepower supply voltage in response to a first positive power supplyapplied to said first power-supply-voltage terminal wherein said secondpower supply voltage is connected to said second power-supply-voltageterminal, and where said second positive power supply voltage is greaterthan said first power supply voltage.
 25. An integrated circuitaccording to claim 20, wherein said first analog subsection produces anintermediate analog current that is a syllabically expanded version ofsaid first analog input information signal.
 26. An integrated circuitaccording to claim 25, wherein said first analog subsection includes: avariable gain means for producing said intermediate analog current inresponse to first analog input information signal; and a level detectormeans for producing a gain control signal in response to said firstanalog input information signal; wherein the gain of said variable gainmeans responds to said gain control signal such that said gain isincreased in response to an increase in said first analog inputinformation signal and said gain is decreased in response to a decreasein said first analog input information signal.